The design techniques of shift registers are known in the art. For instance, U.S. Pat. No. 3,610,951 (to Robert, Stamford, el. in 1971) discloses a design shown in FIG. 8. It has six elements formed in a two-stage structure. There are two clock signals clk1 and clk2 of different phases to shift input data by time and deliver through a data output node. FIGS. 9A and 9B illustrate the simulated node waveforms of the art. FIG. 10 shows the clock signal and input/output waveform relationship described in its patent specification. Comparing FIG. 9A with FIG. 10, it indicates that under the same clock signals CLK1 and CLK2 and input signal, the resulting output waveforms are different from those shown in the patent specification (as shown by the circled portions in FIG. 9A). Even using the clock signals shown in FIG. 9B, only a portion of outputs are same (indicated by the left circle for Data-out in FIG. 9B). Based on the simulation on this node, although there is a shift effect for the input signal, whenever the second clock signal (CLK2) has electric potential fluctuation, data output node also changes. Adopting this on the panel display device, the structure does not truly function as shift register. Even if the element is changed to NMOS, the same result occurs. U.S. Pat. No. 3,937,984 (1976) also discloses a similar design as shown in FIG. 11. It has a capacitor C with one terminal connecting to an output node B of this stage. The gate of the MOS with one terminal connecting to output node B is connected to a reference voltage Vd1 which maintains a low (or high) level voltage when the output node does not have signal output on this stage. Taking PMOS as an example, Vd1 must be a low potential to maintain the output at a high level voltage at the non-trigger signal condition. If Vd1 potential were too low, as the source node of the PMOS is connected to the positive voltage Vdd, output signal cannot reach the desired low potential. As shown in FIG. 12 (indicated by a solid circle), in the event that Vd1 potential is not lower enough, while the output signal can reach a lower level, it is easy to be interfered by the clock signals as shown in FIG. 12 (indicated by circles broken lines). Hence another clock signal has to be used to replace the reference potential Vd1 to improve the problem.